FIG. 1 illustrates a flow of a conventional read process.
FIG. 2 is a sequence diagram illustrating the conventional read process.
A conventional system 11 includes a central processing unit (CPU) 12, a memory 14, a switching controller 13, and a device 15.
The CPU 12, the memory 14, and the device 15 are connected to the switching controller 13.
Here, a flow of a process executed from when the CPU 12 issues a read command (process requests by which the device reads data from the memory) from an address (ADDR) 0 to an address 2 until when the device 15 receives initial read data is described. Each time the process is executed by one step, cycles proceed by 1.
The CPU 12 issues the read command for the address 0 to the address 2 to the device 15 (step S1), and the switching controller 13 relays the read command to the device 15 (step S2).
The device 15 issues a read request for the address 0 to the memory 14 (step S3), and the switching controller 13 relays the read request to the memory 14 (step S4). A description of data read from the addresses 1 and 2 is omitted.
The memory 14 returns data of the address 0 to the device 15 as read data (step S5), and the read data is transferred to the switching controller 13.
The switching controller 13 relays the read data to the device 15 (step S6), which then receives the read data.
As illustrated in FIG. 2, when the read command is issued in a cycle 0, the read data of the address 0 reaches the device 15 in a cycle 6.
Namely, with the conventional read process, the number of cycles (First Read Latency) from when the CPU 12 issues the read command until when the device 15 receives the initial read data is 6.
With the conventional read process, the read command, the read request, or the read data passes through 6 paths from when the CPU issues the read command until when the device receives the read data, so that a latency is increased.
Especially, an interface (I/F) serialized to secure a high band has a very high latency in a serial/parallel conversion unit. Therefore, the high latency is noticeably exhibited as performance degradation if a command or data passes through many paths, leading to a problem.
Patent Document 1) Japanese Laid-Open Patent Publication No. 2002-169768